Content Curator | Updated on - Mar 30, 2026

The M.Tech VLSI Design and Embedded System programme at Chalapathi Institute of Engineering and Technology (CIET), Guntur is a 2-year full-time postgraduate degree affiliated to JNTU Kakinada and approved by AICTE. The programme offers a seat intake of 18 students per year and is designed for ECE/EEE graduates seeking specialised expertise in VLSI circuit design, embedded systems, digital signal processing, and hardware-software co-design. Annual tuition fees under the Convenor Quota (Category A) are Rs. 36,500 per annum and under Management Quota (Category B) are Rs. 36,500 per annum (as per 2021-22 fee structure). Admission is primarily through AP PGECET. The programme is popular among ECE graduates aiming for careers in semiconductor companies, embedded systems firms, and defence/space organisations.

Admissions for the 2026-27 academic year are upcoming. AP PGECET 2026 is typically conducted in May-June, with counselling following in July-August 2026. Students are advised to check the official APSCHE website for the latest AP PGECET 2026 schedule. College-level admissions are expected to commence after AP PGECET counselling, tentatively in August 2026.

Key Points

Specialised 2-year M.Tech programme in VLSI and Embedded Systems with a small batch of 18 seats
Affiliated to JNTU Kakinada with curriculum covering VLSI design, FPGA programming, embedded C, RTOS, and digital design
Strong industry relevance with applications in semiconductor, IoT, automotive, and defence sectors
Faculty with research expertise in VLSI and embedded systems
Graduates are well-positioned for roles in semiconductor companies, VLSI design firms, and embedded systems development

Official Link:

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Highlights
Fees
Admission
Scholarships
Cutoff
Ranking
FAQs

Chalapathi Institute of Engineering and Technology Guntur Latest Updates and News

16 Apr, 2026 AP PGECET 2026 exam is scheduled from April 28 to 30, 2026. for M.E/ M.Tech/ M.Pharm/ Pharm.D (PB) admissions. The hall ticket has been released @cets.apsche.ap.gov.in. Read more.

CIET M.Tech (VLSI Design & Embedded System) Fees

The M.Tech VLSI Design and Embedded System programme at CIET has a uniform fee structure with both Convenor and Management Quota fees set at Rs. 36,500 per annum. Over 2 years, the total tuition fee amounts to Rs. 73,000 under both quotas. Hostel facility is available optionally at an additional cost.

Fee Structure

Fee Component	Convenor Quota (Category A)	Management Quota (Category B)
Tuition Fee (per annum)	Rs. 36,500	Rs. 36,500
Tuition Fee (2 years)	Rs. 73,000	Rs. 73,000
Hostel Fee (per annum, optional)	Rs. 70,000	Rs. 70,000
Total Fees (without hostel)	Rs. 73,000	Rs. 73,000

Fee structure shown is based on 2021-22 data from the official CIET website; fees may be revised for 2026-27.
Hostel fee of Rs. 70,000 per annum is optional and not included in Total Fees above.
Fee payment is typically done semester-wise or annually as per university norms.

CIET M.Tech (VLSI Design & Embedded System) Admission 2026

Admissions to M.Tech VLSI Design and Embedded System at CIET are primarily through AP PGECET conducted by APSCHE. Seats are allocated under Convenor Quota (Category A) through centralised counselling and under Management Quota (Category B) directly by the college. GATE-qualified candidates may also be considered and are eligible for AICTE stipend.

College Admission Dates

Event	Tentative Date
AP PGECET 2026 Exam (Tentative)	May-June 2026
AP PGECET 2026 Result (Tentative)	June-July 2026
AP PGECET Counselling (Tentative)	July-August 2026
College Admission / Batch Start (Tentative)	August 2026

Entrance Exam Dates

Exam	Details
AP PGECET 2026	Tentatively May-June 2026 (check apsche.ap.gov.in for official dates)
GATE 2026 (EC/EE paper)	Conducted in February 2026 (results declared in March 2026)

The dates mentioned above are tentative and subject to change.

Eligibility Criteria:

Candidates must hold a B.Tech/B.E. degree in Electronics and Communication Engineering, Electrical and Electronics Engineering, or a related discipline from a recognised university.
Minimum 50% aggregate marks in the qualifying degree (45% for SC/ST candidates).
Must have appeared in AP PGECET 2026 for Convenor Quota seats; GATE score (EC/EE paper) may be considered for Management Quota and stipend eligibility.

Admission Process:

Register and appear for AP PGECET 2026 (or GATE 2026 EC/EE paper).
Participate in APSCHE web counselling for Convenor Quota seat allotment.
For Management Quota, apply directly to CIET with qualifying degree marksheets and GATE/PGECET scorecard.
Submit required documents and pay the prescribed fee to confirm admission.

CIET M.Tech (VLSI Design & Embedded System) Scholarships 2026

M.Tech students at CIET may be eligible for government scholarships and AICTE-sponsored fellowships. GATE-qualified students admitted through Convenor Quota are eligible for a monthly stipend of Rs. 12,400 as per AICTE norms. AP government scholarships are also available for eligible students.

Scholarship Details

Scholarship / Fellowship	Eligibility	Amount
AICTE GATE Stipend	GATE-qualified students admitted through Convenor Quota	Rs. 12,400 per month
AP SC/ST Post-Matric Scholarship	SC/ST students with family income below prescribed limit	Full tuition fee reimbursement
AP BC/EBC/Minority Post-Matric Scholarship	BC/EBC/Minority students with family income below Rs. 1.5 lakh/year	Partial to full tuition fee reimbursement

AICTE stipend is subject to GATE qualification and Convenor Quota admission; students must maintain satisfactory academic performance.
Government scholarships must be applied through the AP Scholarship Portal within the prescribed deadline.

Chalapathi Institute of Engineering and Technology Guntur M.Tech Vlsi Design & Embedded System Ranking

TOI Ranking

#154 out of 175 in India 2025

#7th in Andhra Pradesh

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CIET M.Tech (VLSI Design & Embedded System) FAQs

Ques. What is the seat intake for M.Tech VLSI Design and Embedded System at CIET?

Ans. The approved intake is 18 seats per year, ensuring a focused learning environment with dedicated faculty mentoring and hands-on lab access.

Ques. Which B.Tech branches are eligible for M.Tech VLSI Design and Embedded System at CIET?

Ans. Primarily B.Tech ECE and EEE graduates are eligible. Graduates from related branches like Electronics Engineering and Instrumentation Engineering may also be eligible as per APSCHE norms.

Ques. What topics are covered in the M.Tech VLSI Design and Embedded System curriculum?

Ans. The curriculum covers VLSI circuit design, FPGA programming, embedded C and C++, RTOS (Real-Time Operating Systems), digital signal processing, hardware-software co-design, and advanced semiconductor device physics.

Ques. What career opportunities are available after M.Tech VLSI Design and Embedded System from CIET?

Ans. Graduates can work as VLSI design engineers, embedded systems developers, firmware engineers, and hardware verification engineers in semiconductor companies, automotive electronics firms, IoT companies, and defence/space organisations like ISRO and DRDO.

Ques. Is GATE required for M.Tech VLSI Design and Embedded System admission at CIET?

Ans. GATE is not mandatory but GATE-qualified candidates (EC/EE paper) are eligible for AICTE stipend of Rs. 12,400 per month and may get preference in Convenor Quota counselling. Non-GATE candidates can apply through AP PGECET.

Ques. What is the total fee for M.Tech VLSI Design and Embedded System at CIET?

Ans. The total tuition fee is Rs. 73,000 over 2 years (Rs. 36,500 per annum) under both Convenor and Management Quota, as per 2021-22 data. This is one of the most affordable M.Tech programmes in the region for VLSI specialisation.